/* SPDX-License-Identifier: GPL-2.0+ */
// $Module: reg_CORE_IP_MUX $
// $RegisterBank Version: v1.0.00 $
// $Author:  $
// $Date: Tue, 28 Feb 2023 09:46:47 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  CORE_IP_MUX_REG_GRP_C906_JTAG0_TDO_SEL  0x0
#define  CORE_IP_MUX_REG_GRP_C906_JTAG0_TDI_SEL  0x4
#define  CORE_IP_MUX_REG_GRP_UART2_RTS_SEL  0x8
#define  CORE_IP_MUX_REG_GRP_IIC4_SDA_SEL  0xc
#define  CORE_IP_MUX_REG_GRP_C906_JTAG0_TCK_SEL  0x10
#define  CORE_IP_MUX_REG_GRP_UART2_CTS_SEL  0x14
#define  CORE_IP_MUX_REG_GRP_IIC4_SCL_SEL  0x18
#define  CORE_IP_MUX_REG_GRP_C906_JTAG0_TMS_SEL  0x1c
#define  CORE_IP_MUX_REG_GRP_CAN1_TX_SEL  0x20
#define  CORE_IP_MUX_REG_GRP_UART2_TX_SEL  0x24
#define  CORE_IP_MUX_REG_GRP_IIC7_SDA_SEL  0x28
#define  CORE_IP_MUX_REG_GRP_C906_JTAG0_TRST_X_SEL  0x2c
#define  CORE_IP_MUX_REG_GRP_CAN1_RXD_SEL  0x30
#define  CORE_IP_MUX_REG_GRP_UART2_RX_SEL  0x34
#define  CORE_IP_MUX_REG_GRP_IIC7_SCL_SEL  0x38
#define  CORE_IP_MUX_REG_GRP_C906_JTAG0_SRST_X_SEL  0x3c
#define  CORE_IP_MUX_REG_GRP_UART4_TX_SEL  0x40
#define  CORE_IP_MUX_REG_GRP_SPI1_CS_X_SEL  0x44
#define  CORE_IP_MUX_REG_GRP_IIC0_SDA_SEL  0x48
#define  CORE_IP_MUX_REG_GRP_I2S2_MCLK_SEL  0x4c
#define  CORE_IP_MUX_REG_GRP_UART4_RX_SEL  0x50
#define  CORE_IP_MUX_REG_GRP_SPI3_SCK_SEL  0x54
#define  CORE_IP_MUX_REG_GRP_IIC0_SCL_SEL  0x58
#define  CORE_IP_MUX_REG_GRP_I2S0_SCLK_SEL  0x5c
#define  CORE_IP_MUX_REG_GRP_UART5_TX_SEL  0x60
#define  CORE_IP_MUX_REG_GRP_SPI0_CS_X_SEL  0x64
#define  CORE_IP_MUX_REG_GRP_IIC5_SDA_SEL  0x68
#define  CORE_IP_MUX_REG_GRP_I2S0_WSI_SEL  0x6c
#define  CORE_IP_MUX_REG_GRP_UART5_RX_SEL  0x70
#define  CORE_IP_MUX_REG_GRP_SPI0_SDI_SEL  0x74
#define  CORE_IP_MUX_REG_GRP_IIC5_SCL_SEL  0x78
#define  CORE_IP_MUX_REG_GRP_I2S0_SDI0_SEL  0x7c
#define  CORE_IP_MUX_REG_GRP_UART6_TX_SEL  0x80
#define  CORE_IP_MUX_REG_GRP_SPI0_SDO_SEL  0x84
#define  CORE_IP_MUX_REG_GRP_IIC6_SDA_SEL  0x88
#define  CORE_IP_MUX_REG_GRP_I2S0_SDI1_SEL  0x8c
#define  CORE_IP_MUX_REG_GRP_UART6_RX_SEL  0x90
#define  CORE_IP_MUX_REG_GRP_SPI0_SCK_SEL  0x94
#define  CORE_IP_MUX_REG_GRP_IIC6_SCL_SEL  0x98
#define  CORE_IP_MUX_REG_GRP_I2S0_SDO_SEL  0x9c
#define  CORE_IP_MUX_REG_GRP_UART7_TX_SEL  0xa0
#define  CORE_IP_MUX_REG_GRP_UART4_RTS_SEL  0xa4
#define  CORE_IP_MUX_REG_GRP_I2S0_MCLK_SEL  0xa8
#define  CORE_IP_MUX_REG_GRP_UART7_RX_SEL  0xac
#define  CORE_IP_MUX_REG_GRP_UART4_CTS_SEL  0xb0
#define  CORE_IP_MUX_REG_GRP_PWM4_SEL  0xb4
#define  CORE_IP_MUX_REG_GRP_PWM5_SEL  0xb8
#define  CORE_IP_MUX_REG_GRP_PWM6_SEL  0xbc
#define  CORE_IP_MUX_REG_GRP_PWM7_SEL  0xc0
#define  CORE_IP_MUX_REG_GRP_PWM8_SEL  0xc4
#define  CORE_IP_MUX_REG_GRP_PWM9_SEL  0xc8
#define  CORE_IP_MUX_REG_GRP_PWM10_SEL  0xcc
#define  CORE_IP_MUX_REG_GRP_PWM11_SEL  0xd0
#define  CORE_IP_MUX_REG_GRP_PWM12_SEL  0xd4
#define  CORE_IP_MUX_REG_GRP_PWM13_SEL  0xd8
#define  CORE_IP_MUX_REG_GRP_PWM14_SEL  0xdc
#define  CORE_IP_MUX_REG_GRP_PWM15_SEL  0xe0
#define  CORE_IP_MUX_REG_GRP_PWM16_SEL  0xe4
#define  CORE_IP_MUX_REG_GRP_PWM17_SEL  0xe8
#define  CORE_IP_MUX_REG_GRP_PWM18_SEL  0xec
#define  CORE_IP_MUX_REG_GRP_PWM19_SEL  0xf0
#define  CORE_IP_MUX_REG_GRP_IIC1_SDA_SEL  0xf4
#define  CORE_IP_MUX_REG_GRP_IIC1_SCL_SEL  0xf8
#define  CORE_IP_MUX_REG_GRP_IIC2_SDA_SEL  0xfc
#define  CORE_IP_MUX_REG_GRP_IIC2_SCL_SEL  0x100
#define  CORE_IP_MUX_REG_GRP_IIC3_SDA_SEL  0x104
#define  CORE_IP_MUX_REG_GRP_IIC3_SCL_SEL  0x108
#define  CORE_IP_MUX_REG_GRP_IIC8_SDA_SEL  0x10c
#define  CORE_IP_MUX_REG_GRP_IIC8_SCL_SEL  0x110
#define  CORE_IP_MUX_REG_GRP_IIC9_SDA_SEL  0x114
#define  CORE_IP_MUX_REG_GRP_IIC9_SCL_SEL  0x118
#define  CORE_IP_MUX_REG_GRP_SD2_D2_SEL  0x11c
#define  CORE_IP_MUX_REG_GRP_SPI2_SDI_SEL  0x120
#define  CORE_IP_MUX_REG_GRP_KEY_COL2_SEL  0x124
#define  CORE_IP_MUX_REG_GRP_SD2_D3_SEL  0x128
#define  CORE_IP_MUX_REG_GRP_SPI2_CS_X_SEL  0x12c
#define  CORE_IP_MUX_REG_GRP_KEY_COL3_SEL  0x130
#define  CORE_IP_MUX_REG_GRP_SD2_D1_SEL  0x134
#define  CORE_IP_MUX_REG_GRP_SPI2_SDO_SEL  0x138
#define  CORE_IP_MUX_REG_GRP_KEY_COL1_SEL  0x13c
#define  CORE_IP_MUX_REG_GRP_SD2_D0_SEL  0x140
#define  CORE_IP_MUX_REG_GRP_SPI2_SCK_SEL  0x144
#define  CORE_IP_MUX_REG_GRP_KEY_COL0_SEL  0x148
#define  CORE_IP_MUX_REG_GRP_SD2_CLK_SEL  0x14c
#define  CORE_IP_MUX_REG_GRP_UART1_RTS_SEL  0x150
#define  CORE_IP_MUX_REG_GRP_KEY_ROW0_SEL  0x154
#define  CORE_IP_MUX_REG_GRP_SD2_CMD_SEL  0x158
#define  CORE_IP_MUX_REG_GRP_UART1_CTS_SEL  0x15c
#define  CORE_IP_MUX_REG_GRP_SPI3_SDO_SEL  0x160
#define  CORE_IP_MUX_REG_GRP_KEY_ROW1_SEL  0x164
#define  CORE_IP_MUX_REG_GRP_SPI3_SDI_SEL  0x168
#define  CORE_IP_MUX_REG_GRP_KEY_ROW2_SEL  0x16c
#define  CORE_IP_MUX_REG_GRP_SPI3_CS_X_SEL  0x170
#define  CORE_IP_MUX_REG_GRP_KEY_ROW3_SEL  0x174
#define  CORE_IP_MUX_REG_GRP_DBG_I2C_SCL_SEL  0x178
#define  CORE_IP_MUX_REG_GRP_UART1_TX_SEL  0x17c
#define  CORE_IP_MUX_REG_GRP_SPI1_SCK_SEL  0x180
#define  CORE_IP_MUX_REG_GRP_DBG_I2C_SDA_SEL  0x184
#define  CORE_IP_MUX_REG_GRP_UART1_RX_SEL  0x188
#define  CORE_IP_MUX_REG_GRP_SPI1_SDO_SEL  0x18c
#define  CORE_IP_MUX_REG_GRP_SPI1_SDI_SEL  0x190
#define  CORE_IP_MUX_REG_GRP_I2S1_MCLK_SEL  0x194
#define  CORE_IP_MUX_REG_GRP_CAM_MCLK0_SEL  0x198
#define  CORE_IP_MUX_REG_GRP_CAM_HS0_SEL  0x19c
#define  CORE_IP_MUX_REG_GRP_PWM1_SEL  0x1a0
#define  CORE_IP_MUX_REG_GRP_I2S1_SDO_SEL  0x1a4
#define  CORE_IP_MUX_REG_GRP_CAM_MCLK1_SEL  0x1a8
#define  CORE_IP_MUX_REG_GRP_CAM_VS2_SEL  0x1ac
#define  CORE_IP_MUX_REG_GRP_I2S1_SCLK_SEL  0x1b0
#define  CORE_IP_MUX_REG_GRP_I2S1_WSI_SEL  0x1b4
#define  CORE_IP_MUX_REG_GRP_I2S1_SDI_SEL  0x1b8
#define  CORE_IP_MUX_REG_GRP_WG0_D0_SEL  0x1bc
#define  CORE_IP_MUX_REG_GRP_WG0_D1_SEL  0x1c0
#define  CORE_IP_MUX_REG_GRP_CAM_VS0_SEL  0x1c4
#define  CORE_IP_MUX_REG_GRP_CAM_HS1_SEL  0x1c8
#define  CORE_IP_MUX_REG_GRP_CAM_VS1_SEL  0x1cc
#define  CORE_IP_MUX_REG_GRP_PWM0_SEL  0x1d0
#define  CORE_IP_MUX_REG_GRP_CAM_HS2_SEL  0x1d4
#define  CORE_IP_MUX_REG_GRP_PWM2_SEL  0x1d8
#define  CORE_IP_MUX_REG_GRP_PWM3_SEL  0x1dc
#define  CORE_IP_MUX_REG_PG_PAD_CTRL0  0x1e0
#define  CORE_IP_MUX_REG_PG_PAD_CTRL1  0x1e0
#define  CORE_IP_MUX_REG_PG_PAD_CTRL2  0x1e0
#define  CORE_IP_MUX_REG_PG_PAD_CTRL3  0x1e0
#define  CORE_IP_MUX_REG_PG_PAD_CTRL4  0x1e0
#define  CORE_IP_MUX_REG_PG_PAD_CTRL5  0x1e0
#define  CORE_IP_MUX_REG_PG_PAD_CTRL6  0x1e0
#define  CORE_IP_MUX_REG_PG_PAD_CTRL7  0x1e0
#define  CORE_IP_MUX_REG_PG_PAD_CTRL8  0x1e0
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDO   0x0
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDO_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDO_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDO_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDI   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDI_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDI_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TDI_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_RTS   0x8
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_RTS_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_RTS_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_RTS_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC4_SDA   0xc
#define  CORE_IP_MUX_REG_GRP_SEL_IIC4_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC4_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC4_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TCK   0x10
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TCK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TCK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TCK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_CTS   0x14
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_CTS_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_CTS_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_CTS_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC4_SCL   0x18
#define  CORE_IP_MUX_REG_GRP_SEL_IIC4_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC4_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC4_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TMS   0x1c
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TMS_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TMS_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TMS_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAN1_TX   0x20
#define  CORE_IP_MUX_REG_GRP_SEL_CAN1_TX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAN1_TX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAN1_TX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_TX   0x24
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_TX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_TX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_TX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC7_SDA   0x28
#define  CORE_IP_MUX_REG_GRP_SEL_IIC7_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC7_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC7_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TRST_X   0x2c
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TRST_X_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TRST_X_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_TRST_X_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAN1_RXD   0x30
#define  CORE_IP_MUX_REG_GRP_SEL_CAN1_RXD_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAN1_RXD_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAN1_RXD_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_RX   0x34
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_RX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_RX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART2_RX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC7_SCL   0x38
#define  CORE_IP_MUX_REG_GRP_SEL_IIC7_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC7_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC7_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_SRST_X   0x3c
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_SRST_X_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_SRST_X_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_C906_JTAG0_SRST_X_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_TX   0x40
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_TX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_TX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_TX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_CS_X   0x44
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_CS_X_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_CS_X_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_CS_X_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC0_SDA   0x48
#define  CORE_IP_MUX_REG_GRP_SEL_IIC0_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC0_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC0_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S2_MCLK   0x4c
#define  CORE_IP_MUX_REG_GRP_SEL_I2S2_MCLK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S2_MCLK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S2_MCLK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_RX   0x50
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_RX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_RX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_RX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SCK   0x54
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SCK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SCK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SCK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC0_SCL   0x58
#define  CORE_IP_MUX_REG_GRP_SEL_IIC0_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC0_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC0_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SCLK   0x5c
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SCLK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SCLK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SCLK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART5_TX   0x60
#define  CORE_IP_MUX_REG_GRP_SEL_UART5_TX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART5_TX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART5_TX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_CS_X   0x64
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_CS_X_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_CS_X_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_CS_X_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC5_SDA   0x68
#define  CORE_IP_MUX_REG_GRP_SEL_IIC5_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC5_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC5_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_WSI   0x6c
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_WSI_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_WSI_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_WSI_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART5_RX   0x70
#define  CORE_IP_MUX_REG_GRP_SEL_UART5_RX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART5_RX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART5_RX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SDI   0x74
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SDI_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SDI_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SDI_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC5_SCL   0x78
#define  CORE_IP_MUX_REG_GRP_SEL_IIC5_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC5_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC5_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDI0   0x7c
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDI0_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDI0_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDI0_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART6_TX   0x80
#define  CORE_IP_MUX_REG_GRP_SEL_UART6_TX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART6_TX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART6_TX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SDO   0x84
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SDO_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SDO_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SDO_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC6_SDA   0x88
#define  CORE_IP_MUX_REG_GRP_SEL_IIC6_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC6_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC6_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDI1   0x8c
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDI1_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDI1_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDI1_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART6_RX   0x90
#define  CORE_IP_MUX_REG_GRP_SEL_UART6_RX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART6_RX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART6_RX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SCK   0x94
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SCK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SCK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI0_SCK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC6_SCL   0x98
#define  CORE_IP_MUX_REG_GRP_SEL_IIC6_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC6_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC6_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDO   0x9c
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDO_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDO_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_SDO_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART7_TX   0xa0
#define  CORE_IP_MUX_REG_GRP_SEL_UART7_TX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART7_TX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART7_TX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_RTS   0xa4
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_RTS_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_RTS_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_RTS_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_MCLK   0xa8
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_MCLK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_MCLK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S0_MCLK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART7_RX   0xac
#define  CORE_IP_MUX_REG_GRP_SEL_UART7_RX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART7_RX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART7_RX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_CTS   0xb0
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_CTS_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_CTS_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART4_CTS_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM4   0xb4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM4_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM4_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM4_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM5   0xb8
#define  CORE_IP_MUX_REG_GRP_SEL_PWM5_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM5_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM5_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM6   0xbc
#define  CORE_IP_MUX_REG_GRP_SEL_PWM6_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM6_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM6_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM7   0xc0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM7_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM7_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM7_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM8   0xc4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM8_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM8_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM8_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM9   0xc8
#define  CORE_IP_MUX_REG_GRP_SEL_PWM9_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM9_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM9_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM10   0xcc
#define  CORE_IP_MUX_REG_GRP_SEL_PWM10_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM10_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM10_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM11   0xd0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM11_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM11_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM11_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM12   0xd4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM12_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM12_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM12_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM13   0xd8
#define  CORE_IP_MUX_REG_GRP_SEL_PWM13_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM13_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM13_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM14   0xdc
#define  CORE_IP_MUX_REG_GRP_SEL_PWM14_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM14_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM14_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM15   0xe0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM15_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM15_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM15_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM16   0xe4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM16_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM16_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM16_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM17   0xe8
#define  CORE_IP_MUX_REG_GRP_SEL_PWM17_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM17_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM17_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM18   0xec
#define  CORE_IP_MUX_REG_GRP_SEL_PWM18_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM18_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM18_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM19   0xf0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM19_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM19_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM19_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC1_SDA   0xf4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC1_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC1_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC1_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC1_SCL   0xf8
#define  CORE_IP_MUX_REG_GRP_SEL_IIC1_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC1_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC1_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC2_SDA   0xfc
#define  CORE_IP_MUX_REG_GRP_SEL_IIC2_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC2_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC2_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC2_SCL   0x100
#define  CORE_IP_MUX_REG_GRP_SEL_IIC2_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC2_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC2_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC3_SDA   0x104
#define  CORE_IP_MUX_REG_GRP_SEL_IIC3_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC3_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC3_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC3_SCL   0x108
#define  CORE_IP_MUX_REG_GRP_SEL_IIC3_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC3_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC3_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC8_SDA   0x10c
#define  CORE_IP_MUX_REG_GRP_SEL_IIC8_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC8_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC8_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC8_SCL   0x110
#define  CORE_IP_MUX_REG_GRP_SEL_IIC8_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC8_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC8_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC9_SDA   0x114
#define  CORE_IP_MUX_REG_GRP_SEL_IIC9_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC9_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC9_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_IIC9_SCL   0x118
#define  CORE_IP_MUX_REG_GRP_SEL_IIC9_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_IIC9_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_IIC9_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D2   0x11c
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D2_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D2_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D2_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SDI   0x120
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SDI_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SDI_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SDI_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL2   0x124
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL2_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL2_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL2_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D3   0x128
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D3_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D3_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D3_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_CS_X   0x12c
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_CS_X_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_CS_X_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_CS_X_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL3   0x130
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL3_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL3_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL3_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D1   0x134
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D1_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D1_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D1_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SDO   0x138
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SDO_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SDO_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SDO_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL1   0x13c
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL1_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL1_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL1_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D0   0x140
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D0_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D0_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_D0_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SCK   0x144
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SCK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SCK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI2_SCK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL0   0x148
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL0_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL0_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_COL0_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_CLK   0x14c
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_CLK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_CLK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_CLK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_RTS   0x150
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_RTS_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_RTS_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_RTS_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW0   0x154
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW0_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW0_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW0_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_CMD   0x158
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_CMD_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_CMD_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SD2_CMD_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_CTS   0x15c
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_CTS_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_CTS_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_CTS_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SDO   0x160
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SDO_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SDO_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SDO_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW1   0x164
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW1_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW1_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW1_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SDI   0x168
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SDI_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SDI_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_SDI_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW2   0x16c
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW2_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW2_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW2_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_CS_X   0x170
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_CS_X_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_CS_X_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI3_CS_X_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW3   0x174
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW3_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW3_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_KEY_ROW3_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_DBG_I2C_SCL   0x178
#define  CORE_IP_MUX_REG_GRP_SEL_DBG_I2C_SCL_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_DBG_I2C_SCL_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_DBG_I2C_SCL_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_TX   0x17c
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_TX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_TX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_TX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SCK   0x180
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SCK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SCK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SCK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_DBG_I2C_SDA   0x184
#define  CORE_IP_MUX_REG_GRP_SEL_DBG_I2C_SDA_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_DBG_I2C_SDA_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_DBG_I2C_SDA_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_RX   0x188
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_RX_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_RX_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_UART1_RX_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SDO   0x18c
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SDO_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SDO_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SDO_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SDI   0x190
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SDI_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SDI_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_SPI1_SDI_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_MCLK   0x194
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_MCLK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_MCLK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_MCLK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_MCLK0   0x198
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_MCLK0_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_MCLK0_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_MCLK0_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS0   0x19c
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS0_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS0_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS0_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM1   0x1a0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM1_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM1_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM1_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SDO   0x1a4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SDO_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SDO_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SDO_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_MCLK1   0x1a8
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_MCLK1_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_MCLK1_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_MCLK1_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS2   0x1ac
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS2_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS2_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS2_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SCLK   0x1b0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SCLK_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SCLK_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SCLK_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_WSI   0x1b4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_WSI_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_WSI_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_WSI_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SDI   0x1b8
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SDI_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SDI_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_I2S1_SDI_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_WG0_D0   0x1bc
#define  CORE_IP_MUX_REG_GRP_SEL_WG0_D0_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_WG0_D0_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_WG0_D0_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_WG0_D1   0x1c0
#define  CORE_IP_MUX_REG_GRP_SEL_WG0_D1_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_WG0_D1_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_WG0_D1_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS0   0x1c4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS0_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS0_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS0_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS1   0x1c8
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS1_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS1_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS1_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS1   0x1cc
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS1_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS1_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_VS1_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM0   0x1d0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM0_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM0_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM0_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS2   0x1d4
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS2_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS2_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_CAM_HS2_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM2   0x1d8
#define  CORE_IP_MUX_REG_GRP_SEL_PWM2_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM2_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM2_BITS   0x4
#define  CORE_IP_MUX_REG_GRP_SEL_PWM3   0x1dc
#define  CORE_IP_MUX_REG_GRP_SEL_PWM3_OFFSET 0
#define  CORE_IP_MUX_REG_GRP_SEL_PWM3_MASK   0xf
#define  CORE_IP_MUX_REG_GRP_SEL_PWM3_BITS   0x4
#define  CORE_IP_MUX_REG_MS_GROUP0   0x1e0
#define  CORE_IP_MUX_REG_MS_GROUP0_OFFSET 0
#define  CORE_IP_MUX_REG_MS_GROUP0_MASK   0x1
#define  CORE_IP_MUX_REG_MS_GROUP0_BITS   0x1
#define  CORE_IP_MUX_REG_MS_GROUP1   0x1e0
#define  CORE_IP_MUX_REG_MS_GROUP1_OFFSET 1
#define  CORE_IP_MUX_REG_MS_GROUP1_MASK   0x2
#define  CORE_IP_MUX_REG_MS_GROUP1_BITS   0x1
#define  CORE_IP_MUX_REG_MS_GROUP2   0x1e0
#define  CORE_IP_MUX_REG_MS_GROUP2_OFFSET 2
#define  CORE_IP_MUX_REG_MS_GROUP2_MASK   0x4
#define  CORE_IP_MUX_REG_MS_GROUP2_BITS   0x1
#define  CORE_IP_MUX_REG_MS_GROUP3   0x1e0
#define  CORE_IP_MUX_REG_MS_GROUP3_OFFSET 3
#define  CORE_IP_MUX_REG_MS_GROUP3_MASK   0x8
#define  CORE_IP_MUX_REG_MS_GROUP3_BITS   0x1
#define  CORE_IP_MUX_REG_MS_GROUP4   0x1e0
#define  CORE_IP_MUX_REG_MS_GROUP4_OFFSET 4
#define  CORE_IP_MUX_REG_MS_GROUP4_MASK   0x10
#define  CORE_IP_MUX_REG_MS_GROUP4_BITS   0x1
#define  CORE_IP_MUX_REG_MS_GROUP5   0x1e0
#define  CORE_IP_MUX_REG_MS_GROUP5_OFFSET 5
#define  CORE_IP_MUX_REG_MS_GROUP5_MASK   0x20
#define  CORE_IP_MUX_REG_MS_GROUP5_BITS   0x1
#define  CORE_IP_MUX_REG_MS_GROUP6   0x1e0
#define  CORE_IP_MUX_REG_MS_GROUP6_OFFSET 6
#define  CORE_IP_MUX_REG_MS_GROUP6_MASK   0x40
#define  CORE_IP_MUX_REG_MS_GROUP6_BITS   0x1
#define  CORE_IP_MUX_REG_MS_GROUP7   0x1e0
#define  CORE_IP_MUX_REG_MS_GROUP7_OFFSET 7
#define  CORE_IP_MUX_REG_MS_GROUP7_MASK   0x80
#define  CORE_IP_MUX_REG_MS_GROUP7_BITS   0x1
#define  CORE_IP_MUX_REG_MS_GROUP8   0x1e0
#define  CORE_IP_MUX_REG_MS_GROUP8_OFFSET 8
#define  CORE_IP_MUX_REG_MS_GROUP8_MASK   0x300
#define  CORE_IP_MUX_REG_MS_GROUP8_BITS   0x2
